1. Field of the Invention
The invention relates in general to a control method for a phase locked loop and an associated apparatus, and more particularly to a control method for quickly locking a phase locked loop and an associated apparatus.
2. Description of the Related Art
A phase locked loop that can serve as a clock multiplier or a clock generator. For example, an input clock having a frequency of 10 MHz, can generate an output clock having a frequency of 1 GHz via a phase locked loop, with a predetermine alignment relationship existing between phases of the output clock and the input clock.
FIG. 1 shows a conventional phase locked loop 10 comprising a frequency/phase detector 12, a charge pump 14, a loop filter 16, a voltage-controlled oscillator (VCO) 20, a multi-modulus divisor (MMD) 22, a sigma-delta modulator (SDM) 24, and a bank correction controller 26. Via a step-up signal UP and a step-down signal DN, the frequency/phase detector 12 sends a relationship associated with frequencies and phases of a reference signal FREF and a feedback signal FDIV. The charge pump 14 then provides a charging/discharging current according to the relationship. The loop filter 16 substantially collects results of the charging/discharging, and generates a control signal VCTRL to control a high-frequency oscillation signal FVCO outputted by the VCO 20. The MMD 22 steps down the oscillation signal FVCO to generate the feedback signal FDIV. The SDM 24 generates a current divisor signal PIN according to a desired divisor consisted of an integral signal NINT and a fraction signal NFRAC to determine a frequency divisor NDIV to be executed by the MMD 22. With a signal loop provided by the frequency/phase divisor 12, the charge pump 14, the loop filter 16, the VCO 20, and the MMD 22, the phase of the feedback signal FDIV is enabled to substantially follow the phase of the reference signal FREF.
To reduce noise generated by the phase locked loop, a voltage-to-frequency gain of the VCO 20 during operations is designed to be low. To improve a narrow lockable range resulted by the low gain, the VCO 20 is designed with several banks each providing a corresponding lockable range. FIG. 2 shows an operation time sequence of the phase locked loop 10. The bank correction controller initially fixes a voltage of the control signal VCTRL at a voltage value VREF to equivalently open the phase locked loop 10, and then performs correction bank by bank in a bank correction 27. During the bank correction 27, the bank correction controller 26 checks a relationship between the oscillation signal FVCO and the reference signal FREF, and selects a bank on which the VCO 20 operates according to a selection signal BS.
After the banks for the VCO 20 are confirmed, the frequencies of the reference signal FREF and the feedback signal FDIV approximating each other, and a close loop locking 29 performed. The bank correction controller 26 disengages the control signal VCTRL from the clamping of the voltage value VREF, such that the phase locked loop 10 becomes closed to allow the phase of the feedback signal FDIV to follow the phase of the reference signal FREF having an approximate frequency. A period from the phase locked loop being closed to being locked is defined as a lock time.
FIG. 3 shows a conventional frequency/phase detector 12. Although the frequencies of the reference signal FREF and the feedback signal FDIV already fall within approximate ranges after the banks within are confirmed, the phases of the reference signal FREF and the feedback signal FDIV may yet be quite different, with a maximum difference possibly being as large as 360 degrees. FIG. 4 shows a possible signal timing diagram, in which from top to bottom are the reference signal FREF, the feedback signal FDIV, the step-up signal UP, and the step-down signal DN. In FIG. 4, the phase of the feedback signal FDIV falls behind that of the reference signal FREF by almost 360 degrees. Therefore, in a references cycle of the reference signal FREF, the step-up signal UP is at logic 1 most of the time.
When a phase difference gets large, the large phase difference is inclined to cause an increased lock time despite that the frequencies of the reference signal FREF and the feedback signal FDIV approximate each other, such that the increased lock time may exceed a lock time limit demanded by a system. FIG. 5 shows a corresponding control signal VCTRL possibly generated in response to the signals in FIG. 4. Since the step-up signal UP is mostly at logic 1, the control signal VCTRL quickly reaches a non-linear, saturated high point once the phase locked loop becomes closed and locked. At this point, the frequency of the feedback signal FDIV is slightly higher than that of the reference signal FREF, and so a rising edge of the feedback signal FDIV gradually approximates a rising edge of the reference signal FREF until a delayed part in the phase is made up—such process is referred to as non-linear settling. The control signal VCTRL then returns to linearity so that the frequency of the feedback signal FDIV approximates that of the reference signal FREF—such a process is referred to as linear settling. In short, a locking time TLOCK is a total time of a time TNON-LINEAR required for non-linear settling and a time TLINEAR required for linear settling. TNON-LINEAR may be roughly calculated by an equation (1) below.
                                                                        T                                  NON                  ⁢                                      -                                    ⁢                  LINEAR                                            =                            ⁢                                                (                                      1                    ⁢                                          /                                        ⁢                                          (                                                                        f                          REF                                                *                                                  f                          DIV                                                                    )                                                        )                                /                                  (                                                            1                      ⁢                                              /                                            ⁢                                              f                        DIV                                                              -                                          1                      ⁢                                              /                                            ⁢                                              f                        REF                                                                              )                                                                                                        =                            ⁢                              1                ⁢                                  /                                ⁢                                  (                                                            f                      DIV                                        -                                          f                      REF                                                        )                                                                                                        =                            ⁢                                                N                  DIV                                ⁢                                  /                                ⁢                Δ                ⁢                                                                  ⁢                                  f                  VCO                                                                                        (        1        )            
In the equation (1), fREF and fDIV are respectively frequencies of the reference signal FREF and the feedback signal FDIV, NDIV is a divisor when the MMD 22 performs close loop locking, and ΔfVCO is a possible maximum frequency difference of the VCO 20 for a current bank. For example, when ΔfVCO is around 3.978 GHz, FREF is around 26 MHz and ΔfVCO is around 1 MHz, TNON-LINEAR equals (3978/26)/1, which is as high as 153 μs. The rather long period of the TNON-LINEAR is likely to exceed a predetermined tolerance of a system that has a set limit for the lock time, in a way that the system may fail to meet standardized specifications. For example, for communication systems including Global System for Mobile Communications (GSM), Bluetooth, Wireless Fidelity (WiFi) implementing burst transmission that switches among channels, a limit of the lock time TLOCK is defined, which means the above excessive TNON-LINEAR required for non-linear settling is unacceptable.